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<title>CVTDQ2PD—Convert Packed Doubleword Integers to Packed Double-Precision Floating-Point Values </title></head>
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<h1>CVTDQ2PD—Convert Packed Doubleword Integers to Packed Double-Precision Floating-Point Values</h1>
<table>
<tr>
<th>Opcode/Instruction</th>
<th>Op /En</th>
<th>64/32 bit Mode Support</th>
<th>CPUID Feature Flag</th>
<th>Description</th></tr>
<tr>
<td>F3 0F E6 /r CVTDQ2PD xmm1, xmm2/m64</td>
<td>RM</td>
<td>V/V</td>
<td>SSE2</td>
<td>Convert two packed signed doubleword integers from xmm2/mem to two packed double-precision floating-point values in xmm1.</td></tr>
<tr>
<td>VEX.128.F3.0F.WIG E6 /r VCVTDQ2PD xmm1, xmm2/m64</td>
<td>RM</td>
<td>V/V</td>
<td>AVX</td>
<td>Convert two packed signed doubleword integers from xmm2/mem to two packed double-precision floating-point values in xmm1.</td></tr>
<tr>
<td>VEX.256.F3.0F.WIG E6 /r VCVTDQ2PD ymm1, xmm2/m128</td>
<td>RM</td>
<td>V/V</td>
<td>AVX</td>
<td>Convert four packed signed doubleword integers from xmm2/mem to four packed double-precision floating-point values in ymm1.</td></tr>
<tr>
<td>EVEX.128.F3.0F.W0 E6 /r VCVTDQ2PD xmm1 {k1}{z}, xmm2/m128/m32bcst</td>
<td>HV</td>
<td>V/V</td>
<td>AVX512VL AVX512F</td>
<td>Convert 2 packed signed doubleword integers from xmm2/m128/m32bcst to eight packed double-precision floating-point values in xmm1 with writemask k1.</td></tr>
<tr>
<td>EVEX.256.F3.0F.W0 E6 /r VCVTDQ2PD ymm1 {k1}{z}, xmm2/m128/m32bcst</td>
<td>HV</td>
<td>V/V</td>
<td>AVX512VL AVX512F</td>
<td>Convert 4 packed signed doubleword integers from xmm2/m128/m32bcst to 4 packed double-precision floating-point values in ymm1 with writemask k1.</td></tr>
<tr>
<td>EVEX.512.F3.0F.W0 E6 /r VCVTDQ2PD zmm1 {k1}{z}, ymm2/m256/m32bcst</td>
<td>HV</td>
<td>V/V</td>
<td>AVX512F</td>
<td>Convert eight packed signed doubleword integers from ymm2/m256/m32bcst to eight packed double-precision floating-point values in zmm1 with writemask k1.</td></tr></table>
<h3>Instruction Operand Encoding</h3>
<table>
<tr>
<td>Op/En</td>
<td>Operand 1</td>
<td>Operand 2</td>
<td>Operand 3</td>
<td>Operand 4</td></tr>
<tr>
<td>RM</td>
<td>ModRM:reg (w)</td>
<td>ModRM:r/m (r)</td>
<td>NA</td>
<td>NA</td></tr>
<tr>
<td>HV</td>
<td>ModRM:reg (w)</td>
<td>ModRM:r/m (r)</td>
<td>NA</td>
<td>NA</td></tr></table>
<h2>Description</h2>
<p>Converts two, four or eight packed signed doubleword integers in the source operand (the second operand) to two, four or eight packed double-precision floating-point values in the destination operand (the first operand).</p>
<p>EVEX encoded versions: The source operand can be a YMM/XMM/XMM (low 64 bits) register, a 256/128/64-bit memory location or a 256/128/64-bit vector broadcasted from a 32-bit memory location. The destination operand is a ZMM/YMM/XMM register conditionally updated with writemask k1. Attempt to encode this instruction with EVEX embedded rounding is ignored.</p>
<p>VEX.256 encoded version: The source operand is an XMM register or 128- bit memory location. The destination operand is a YMM register.</p>
<p>VEX.128 encoded version: The source operand is an XMM register or 64- bit memory location. The destination operand is a XMM register. The upper Bits (MAX_VL-1:128) of the corresponding ZMM register destination are zeroed.</p>
<p>128-bit Legacy SSE version: The source operand is an XMM register or 64- bit memory location. The destination operand is an XMM register. The upper Bits (MAX_VL-1:128) of the corresponding ZMM register destination are unmodified.</p>
<p>VEX.vvvv and EVEX.vvvv are reserved and must be 1111b, otherwise instructions will #UD.</p>
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<h3>Figure 3-11.  CVTDQ2PD (VEX.256 encoded version)</h3>
<h2>Operation</h2>
<p><strong>VCVTDQ2PD (EVEX encoded versions) when src operand is a register</strong></p>
<pre>(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j (cid:197) 0 TO KL-1
    i (cid:197) j * 64
    k (cid:197) j * 32
    IF k1[j] OR *no writemask*
         THEN DEST[i+63:i] (cid:197)
              Convert_Integer_To_Double_Precision_Floating_Point(SRC[k+31:k])
         ELSE
              IF *merging-masking*
                                                         ; merging-masking
                    THEN *DEST[i+63:i] remains unchanged*
                    ELSE
                                                         ; zeroing-masking
                         DEST[i+63:i] (cid:197) 0
              FI
    FI;
ENDFOR
DEST[MAX_VL-1:VL] (cid:197) 0</pre>
<p><strong>VCVTDQ2PD (EVEX encoded versions) when src operand is a memory source</strong></p>
<pre>(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j (cid:197) 0 TO KL-1
    i (cid:197) j * 64
    k (cid:197) j * 32
    IF k1[j] OR *no writemask*
         THEN
              IF (EVEX.b = 1)
                    THEN
                         DEST[i+63:i] (cid:197)
              Convert_Integer_To_Double_Precision_Floating_Point(SRC[31:0])
                    ELSE
                         DEST[i+63:i] (cid:197)
              Convert_Integer_To_Double_Precision_Floating_Point(SRC[k+31:k])
              FI;
         ELSE
              IF *merging-masking*
                                                         ; merging-masking
                    THEN *DEST[i+63:i] remains unchanged*
                    ELSE
                                                         ; zeroing-masking
                         DEST[i+63:i] (cid:197) 0
              FI
    FI;
ENDFOR
DEST[MAX_VL-1:VL] (cid:197) 0</pre>
<p><strong>VCVTDQ2PD (VEX.256 encoded version)</strong></p>
<pre>DEST[63:0] (cid:197) Convert_Integer_To_Double_Precision_Floating_Point(SRC[31:0])
DEST[127:64] (cid:197) Convert_Integer_To_Double_Precision_Floating_Point(SRC[63:32])
DEST[191:128] (cid:197) Convert_Integer_To_Double_Precision_Floating_Point(SRC[95:64])
DEST[255:192] (cid:197) Convert_Integer_To_Double_Precision_Floating_Point(SRC[127:96)
DEST[MAX_VL-1:256] (cid:197) 0</pre>
<p><strong>VCVTDQ2PD (VEX.128 encoded version)</strong></p>
<pre>DEST[63:0] (cid:197) Convert_Integer_To_Double_Precision_Floating_Point(SRC[31:0])
DEST[127:64] (cid:197) Convert_Integer_To_Double_Precision_Floating_Point(SRC[63:32])
DEST[MAX_VL-1:128] (cid:197) 0</pre>
<p><strong>CVTDQ2PD (128-bit Legacy SSE version)</strong></p>
<pre>DEST[63:0] (cid:197) Convert_Integer_To_Double_Precision_Floating_Point(SRC[31:0])
DEST[127:64] (cid:197) Convert_Integer_To_Double_Precision_Floating_Point(SRC[63:32])
DEST[MAX_VL-1:128] (unmodified)</pre>
<h2>Intel C/C++ Compiler Intrinsic Equivalent</h2>
<p>VCVTDQ2PD __m512d _mm512_cvtepi32_pd( __m256i a);</p>
<p>VCVTDQ2PD __m512d _mm512_mask_cvtepi32_pd( __m512d s, __mmask8 k, __m256i a);</p>
<p>VCVTDQ2PD __m512d _mm512_maskz_cvtepi32_pd( __mmask8 k, __m256i a);</p>
<p>VCVTDQ2PD __m256d _mm256_mask_cvtepi32_pd( __m256d s, __mmask8 k, __m256i a);</p>
<p>VCVTDQ2PD __m256d _mm256_maskz_cvtepi32_pd( __mmask8 k, __m256i a);</p>
<p>VCVTDQ2PD __m128d _mm_mask_cvtepi32_pd( __m128d s, __mmask8 k, __m128i a);</p>
<p>VCVTDQ2PD __m128d _mm_maskz_cvtepi32_pd( __mmask8 k, __m128i a);</p>
<p>CVTDQ2PD __m256d _mm256_cvtepi32_pd (__m128i src)</p>
<p>CVTDQ2PD __m128d _mm_cvtepi32_pd (__m128i src)</p>
<h2>Other Exceptions</h2>
<table class="exception-table">
<tr>
<td>VEX-encoded instructions, see Exceptions Type 5;</td></tr>
<tr>
<td>EVEX-encoded instructions, see Exceptions Type E5.</td></tr>
<tr>
<td>If VEX.vvvv != 1111B or EVEX.vvvv != 1111B.</td></tr></table></body></html>